In today’s electronic engineering landscape, the demand for high-speed design has never been higher. With interfaces like USB-C, WIFI, DDR, MIPI, and others becoming cornerstones of tomorrow’s products, designers need to have an understanding of what high-speed signals are and the challenges they pose.
In this series we will delve into some of the important considerations required to make these designs successful.
Welcome back to our series on High Speed PCB design. In the previous article, we explored the importance of setting up your design environment to facilitate routing. In this article, we will provide 4 tips to optimize for high speed design – including the “whys and hows” – so you can use them effectively in your next design.
Minimize Cross Talk
Crosstalk is an unintended electromagnetic coupling between signal traces or wires, resulting in interference or noise on adjacent lines. This occurs when an electrical signal in one trace (the aggressor) induces unwanted voltage or current in a nearby trace (the victim) due to capacitive or inductive coupling. It tends to occur when the aggressor signal runs parallel to the victim for an extended length.
The goal should be: limit crosstalk to 3% or -30dB. Defining exactly what spacings are required to achieve that can be complex because the variables are interrelated:
- Trace clearance
- Signal frequency
- Coupled length
- Distance to reference plane
There are many calculators out there such as the PCB Design Toolkit from Saturn PCB. These will allow you to explore combinations that keep crosstalk below the 3% threshold.
Be Sure to Length Match
When frequency is high enough, the travel-time of an electron along a trace becomes relevant. Signals that are meant to be received together arrive at different times, resulting in timing errors, signal integrity issues, and data corruption. This is particularly important in interfaces like DDR memory, PCIe, and high-speed serial communication, where precise timing is crucial. The goal is to make sure that parallel traces of the same data-bus are almost exactly the same length.
Length matching is usually expressed as a percentage of the signal’s wavelength. The goal should be: Length-Match to within 10% of the signal wavelength.
You can also approach this measurement by examining the time delay. Ensure that the skew is within 50-100 picoseconds for most interfaces, and tighter for faster designs. As each interface has its own constraints, its important to check the device datasheet or interface standard for specifics on timing requirements.
Examples of Porticos projects utilizing PCB layouts.
Minimize Vias Stubs
Via stubs can be a source of unwanted reflections.
The goal should be: Address stub length if it is greater than 5% of the signal wavelength.
Take, for example, a 10G ethernet signal that is routed on a standard 1.5mm FR4 board. Using the wavelength equation given in the first article of our series, the wavelength of the signal can be determined to be 14mm and thus a stub greater than 0.7mm could begin to cause interference. Luckily, there are several simple techniques to mitigate this.
This diagram shows a 12-layer stackup with different via constructions. Let’s consider the example of a signal that starts and ends on a top layer but needs to be routed internally. For a standard PCB with only through-hole vias, it is advantageous to route that layer on L10 instead of L3 because it will reduce the size of the stub. If the designer has access to more sophisticated structures such as blind vias, buried vias, or back drilling, these can be used strategically to reduce or completely eliminate stubs, though at a cost.
Use Curved Traces
When routing a high speed trace, consider using curved traces. Curving traces helps make the impedance of the trace consistent along its length. Even 45 degree corners can cause significant changes in impedance and create reflections that can lead to distortion of the signal. Modern fabrication processes make curved traces very cost-effective, so there is little reason not to use them.
The goal should be: Always use curved traces for RF signals above 1 GHz, for edges faster than 100 ps, or for data exceeding 10 GBPS.
Conclusion
None of these ingredients are especially complex, but missing or miscalculating even one of them can lead to unacceptable performance. Follow these tips to find success in your next PCB layout.
Have you finished the layout? Ready for the Design Review? Stay tuned for part 4 of our series, covering five common mistakes in high-speed design. And if you’re running into trouble with your own PCB project, remember that Porticos has a team of engineers to help you with your design and implementation. Get in touch to learn more.
