In today’s electronic engineering landscape, the demand for high-speed design has never been higher. With interfaces like USB-C, WIFI, DDR, MIPI, and others becoming cornerstones of tomorrow’s products, designers need to have an understanding of what high-speed signals are and the challenges they pose.
In this series we will delve into some of the important considerations required to make these designs successful.
In the previous article, High Speed PCB Layouts: An Introduction, we explored what constitutes high-speed design and some of the key challenges involved. In this article, we’ll delve into setting up your design environment for a successful high-speed PCB (printed circuit board) layout. Achieving success in high-speed design requires meticulous planning and thoughtful execution, as the complexity demands attention to every detail from the outset.
Establishing Net Classes
Firstly, it’s important to understand what you are working with. There are many different types of high-speed signals including USB data lines, DDR busses, and RF connections. Each will require a slightly different treatment.
The first step is identifying these high-speed signals and organizing them into “net classes.” Net classes are logical groupings of nets (electrical connections) that allow a designer to manage nets efficiently. Creating net classes in this stage allows the designer to plan constraints more effectively and also helps them anticipate what some of the overarching challenges of the design will be.
Net Classes can be defined in the schematic or on the layout depending on the tool and the preferences of the designers. It’s important to discuss this among the team to determine how and where to make these definitions so things don’t fall through the cracks.
Choosing a Stackup Architecture
The next step is choosing an architecture for the arrangement of copper and insulating layers that make up your PCB. This arrangement of materials is referred to as a “stackup”, and selecting the right architecture is a multifaceted problem requiring consideration of many factors including copper weight, number of layers, and total board thickness.
To start, we recommend selecting the number of layers. This is usually driven by routing complexity, BGA (Ball Grid Array) connection “fanouts”, and overall density. It’s important to take high-speed requirements into account during this process. Any layer that will support high-speed traces should ideally have two reference planes on either side. This can add extra plane layers and increase the total layer count, but the inclusion can help mitigate problems down the line. Below is an example of a 12-layer, high-speed stackup. You can see that all internal routing layers are shielded by planes on both sides.
After the layer stack has been determined, the dielectric material(s) must be selected. Most standard PCBs are made using FR-4, however, when it comes to high speed, regular FR4 may not be up to the task. Selecting a high-performance dielectric such as ISOLA FR408HR, PTFE, or even a high-speed variant of FR-4 can provide many benefits including faster propagation, lower losses, and smaller trace widths, among others. Selecting this material early in the layout process is critical because it will affect impedance traces, a critical aspect of high-speed PCB design that provides specific, controlled impedance of the signal. This can ensure signal integrity, electromagnetic compatibility, and performance for high-frequency layouts.
We recommend engaging your PCB manufacturer at this stage. They can help provide useful information such as recommending dielectrics, physical constraints, and complete stackups that align with their process. This can help reduce overall cost and churn when the design is being handed off for fabrication.
Examples of Porticos projects utilizing PCB layouts.
Defining Impedance Profiles
Once the stackup has been finalized, the next step is to create impedance profiles for all controlled impedance requirements. The profiles define trace width and reference layers for each impedance requirement.
Different high speed signals have different impedance requirements. RF traces are typically expected to be 50 Ohms and USB data lines are expected to be 90 Ohm differential. Impedance profiles can be set up for each impedance requirement so that trace widths and differential pair spacing can be constrained before routing begins.
Conclusion
High Speed PCB layout is a complicated undertaking but like any complex task, laying the proper foundation will help deliver successful results in the end. Porticos can help you get there with expertise in electronics and hardware engineering.
Is your design environment all set up for routing? Check out part 3 of our series with 7 Routing Tips for High Speed PCB Design to use for your next PCB layout.
